CMOS latch bit-cell array for low-power SRAM design
نویسندگان
چکیده
منابع مشابه
A Design of Sram Structure for Low Power Using Heterojunction Cmos with Single Bit Line
The Present day workstations, low-power processors, computers and super computers are using fast Static Random Access Memory (SRAMs) and will require, in the future, larger density memories with faster access time and minimum power consumption. Acknowledging the intense requirements for power, in current high performance memories of computing devices, the circuit designers have developed a numb...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2010
ISSN: 1349-2543
DOI: 10.1587/elex.7.1145